View MT4C16270_3054619.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. dram 256k x 16 dram 5v, edo page mode features ? industry-standard x16 pinouts, timing, functions and packages ? high-performance cmos silicon-gate process ? single +5v 10% power supply* ? low power, 3mw standby; 300mw active, typical ? all device pins are ttl-compatible ? 512-cycle refresh in 8ms (9 row- and 9 column addresses) ? refresh modes: ras#-only, cas#-before-ras# (cbr) and hidden ? extended data-out (edo) page mode access cycle ? byte write and byte read access cycles options marking ? timing 40ns access -4* 50ns access -5* 60ns access -6 ? packages plastic soj (400 mil) dj ? part number example: MT4C16270dj-4 *40ns and 50ns access specifications are limited to a v cc range of 5%. contact factory for availability. pin assignment (top view) 40-pin soj (da-6) vcc dq1 dq2 dq3 dq4 vcc dq5 dq6 dq7 dq8 nc nc we# ras# nc a0 a1 a2 a3 vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vss dq16 dq15 dq14 dq13 vss dq12 dq11 dq10 dq9 nc casl# cash# oe# a8 a7 a6 a5 a4 vss key timing parameters speed t rc t rac t pc t aa t cac t cas t cp -4 75ns 40ns 15ns 20ns 12ns 6ns 6ns -5 100ns 50ns 20ns 25ns 15ns 8ns 8ns -6 110ns 60ns 25ns 30ns 15ns 10ns 10ns casl# or cash# will generate an internal cas#. use of only one of the two results in a byte write cycle. casl# transitioning low selects a write cycle for the lower byte (dq1-dq8) and cash# transitioning low selects a write cycle for the upper byte (dq9-dq16). byte read cycles are achieved through casl# or cash# in the same manner. general description the MT4C16270 is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x16 con- figuration. the MT4C16270 has both byte write and word write access cycles via two cas# pins. the MT4C16270 cas# function and timing are deter- mined by the first cas# (casl# or cash#) to transition low and by the last to transition back high. casl# and cash# function in a similar manner to cas# in that either
2 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. functional block diagram casl# cas# ras# 9 9 no. 2 clock generator refresh controller no. 1 clock generator 512 x 512 x 16 memory array vcc vss 9 oe# dq1 dq16 refresh counter cash# a0 a1 a2 a3 a4 a5 a6 a7 a8 8 512 512 x 16 16 9 512 we# 8 16 control logic sense amplifiers i/o gating data-out buffer data-in buffer column- address buffer row- address buffers (9) 9 row decoder column decoder functional description each bit is uniquely addressed through the 18 address bits during read or write cycles. these are entered 9 bits (a0 -a8) at a time. ras# is used to latch the first 9 bits and cas# the latter 9 bits. the cas# control also determines whether the cycle will be a refresh cycle (ras#-only) or an active cycle (read, write or read write) once ras# goes low. the MT4C16270 has two cas# controls, casl# and cash#. the casl# and cash# inputs internally generate a cas# signal functioning in a similar manner to the single cas# input on the other 256k x 16 drams. the key difference is that each cas# controls its corresponding dq tristate logic (in conjunction with oe# and we# and ras#). casl# controls dq1 through dq8 and cash# controls dq9 through dq16. the MT4C16270 cas# function is determined by the first cas# (casl# or cash# ) transitioning low and the last transitioning back high. the two cas# controls give the MT4C16270 both byte read and byte write cycle capa- bilities. (see figure 2.) a logic high on we# dictates read mode while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we or cas# (casl# or cash#), whichever occurs last. an early write occurs when we is taken low prior to either cas# falling. a late write or read-modify-write occurs when we falls after cas# (casl# or cash#) was taken low. during early write cycles, the data-outputs (q) will remain high-z regardless of the state of oe#. during late write or read-modify-write cycles, oe# must
3 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. figure 2 word and byte read example figure 1 word and byte write example stored data 1 1 0 1 1 1 1 1 ras# casl# we# z = high-z address 1 address 0 0 1 0 1 0 0 0 0 word read lower byte read stored data 1 1 0 1 1 1 1 1 cash# output data 1 1 0 1 1 1 1 1 stored data 1 1 0 1 1 1 1 1 z z z z z z z z output data 1 1 0 1 1 1 1 1 output data 1 1 0 1 1 1 1 1 output data 1 1 0 1 1 1 1 1 stored data 1 1 0 1 1 1 1 1 upper byte (dq9-dq16) of word lower byte (dq1-dq8) of word 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 z z z z z z z z z z z z z z z z 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 stored data 1 1 0 1 1 1 1 1 ras# casl# we# x = not effective (don t care) address 1 address 0 0 1 0 1 0 0 0 0 word write lower byte write cash# input data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 x x x x x x x x input data 1 1 0 1 1 1 1 1 input data stored data 1 1 0 1 1 1 1 1 input data stored data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 stored data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 x x x x x x x x 1 0 1 0 1 1 1 1 upper byte (dq9-dq16) of word lower byte (dq1-dq8) of word
4 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. functional description (continued) be taken high to disable the data-outputs prior to apply- ing input data. if a late write or read-modify- write is attempted while keeping oe# low, no write will occur, and the data-outputs will drive read data from the accessed location. additionally, both bytes must always be of the same mode of operation if both bytes are active. a cas# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. for example, an early write on one byte and a late write on the other byte is not allowed during the same cycle. however, an early write on one byte and, after a cas# precharge has been satisfied, a late write on the other byte is permissable. the 16 data inputs and 16 data outputs are routed through 16 pins using common i/o, and pin direction is controlled by oe#, we# and ras#. edo page mode operations allow faster data opera- tions (read, write or read-modify-write) within a row-address-defined (a0 -a8) page boundary. the edo page mode cycle is always initiated with a row address strobed-in by ras# followed by a column address strobed-in by cas#. cas# may be toggled by holding ras# low and strobing-in different column-addresses, thus executing faster memory cycles. returning ras# high terminates the edo page mode operation. byte access cycle the byte write cycle is determined by the use of casl# and cash#. enabling casl# will select a lower byte write cycle (dq1-dq8) while enabling cash# will select an upper byte write cycle (dq9-dq16). enabling both casl# and cash# selects a word write cycle. the MT4C16270 can be viewed as two 256k x 8 drams which have common input controls. figure 1 illustrates the MT4C16270 byte write and word write cycles. the byte read is accomplished in the same manner. v v ih il casl#/cash# v v ih il ras# v v ih il addr row column (a) column (b) don? care undefined v v ih il oe# v v ioh iol open dq t od valid data (b) valid data (a) column (c) valid data (a) t oe valid data (c) column (d) valid data (d) t od t oehc t od t oep t oes the dqs go back to low-z if t oes is met. the dqs remain high-z until the next cas# cycle if t oehc is met. the dqs remain high-z until the next cas# cycle if t oep is met. figure 3 output enable and disable
5 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. v v ih il v v ih il ras# v v ih il addr row column (a) don? care undefined v v ih il we# v v ioh iol open dq t wpz the dqs go to high-z if we# falls, and if t wpz is met, will remain high-z until cas# goes low with we# high (i.e., until a read cycle is initiated). v v ih il oe# valid data (b) t whz we# may be used to disable the dqs to prepare for input data in an early write cycle. the dqs will remain high-z until cas# goes low with we# high (i.e., until a read cycle is initiated). t whz column (d) valid data (a) column (b) column (c) input data (c) casl#/cash# figure 4 output enable and disable with we# transitions high. then oe# can pulse high for a mini- mum of t oep anytime during the cas# high period and the dqs will tristate and remain tristate, regardless of oe#, until cas# falls again (please reference figure 3 for further detail on the toggling oe# condition). during other cycles, the outputs are disabled at t off time after ras# and cas# are high, or t whz after we# transitions low. the t off time is referenced from the rising edge of ras# or cas#, whichever occurs last. we# can also perform the function of turning off the output drivers under certain conditions, as shown in figure 4. returning ras# and cas# high terminates a memory cycle and decreases chip current to a reduced standby level. the chip is also preconditioned for the next cycle during the ras# high time. memory cell data is retained in its correct state by maintaining power and executing any ras# cycle (read, write) or ras# refresh cycle (ras#-only, cbr, or hidden) so that all 512 combinations of ras# ad- dresses (a0 -a8) are executed at least every 8ms, regardless of sequence. the cbr refresh cycle will also invoke the refresh counter and controller for row address control. edo page mode dram read cycles have traditionally turned the out- put buffers off (high-z) with the rising edge of cas#. if cas# goes high, and oe# is low (active), the output buffers will be disabled. the MT4C16270 offers an acceler- ated page mode cycle by eliminating output disable from cas# high. this option is called edo and it allows cas# precharge time ( t cp) to occur without the output data going invalid (see read and edo-page-mode read wave- forms). edo operates as any dram read or fast-page- mode read, except data will be held valid after cas# goes high, as long as ras# and oe# are held low and we# is held high. oe# can be brought low or high while cas# and ras# are low, and the dqs will transi- tion between valid data and high-z. using oe#, there are two methods to disable the outputs and keep them disabled during the cas# high time. the first method is to have oe# high when cas# transitions high and keep oe# high for t oehc. this will tristate the dqs and they will remain tristate, regardless of oe#, until cas# falls again. the second method is to have oe# low when cas#
6 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. truth table addresses function ras# casl# cash# we# oe# t r t c dqs notes standby h h ? xh ? x x x x x high-z read: word l l l h l row col data-out read: lower byte l l h h l row col lower byte, data-out upper byte, high-z read: upper byte l h l h l row col lower byte, high-z upper byte, data out write: word l l l l x row col data-in (early write) write: lower l l h l x row col lower byte, data-in byte (early) upper byte, high-z write: upper l h l l x row col lower byte, high-z byte (early) upper byte, data-in read write l l l h ? ll ? h row col data-out, data-in 1, 2 edo-page- 1st cycle l h ? lh ? l h l row col data-out 2 mode read 2nd cycle l h ? lh ? l h l n/a col data-out 2 any cycle l l ? hl ? h h l n/a n/a data-out 2 edo-page- 1st cycle l h ? lh ? l l x row col data-in 1 mode write 2nd cycle l h ? lh ? l l x n/a col data-in 1 edo- 1st cycle l h ? lh ? lh ? ll ? h row col data-out, data-in 1, 2 page-mode 2nd cycle l h ? lh ? lh ? ll ? h n/a col data-out, data-in 1, 2 read-write hidden read l ? h ? l l l h l row col data-out 2 refresh write l ? h ? l l l l x row col data-in 1, 3 ras#-only refresh l h h x x row n/a high-z cbr refresh h ? l l l x x x x high-z 4 note: 1. these write cycles may also be byte write cycles (either casl# or cash# active). 2. these read cycles may also be byte read cycles (either casl# or cash# active). 3. early write only. 4. at least one of the two cas# signals must be active (casl# or cash#).
7 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. parameter/conditions symbol -4 -5 -6 units notes standby current: (ttl) i cc 1 222ma (ras# = cas# = v ih ) standby current: (cmos) i cc 2 111ma25 (ras# = cas# = v cc -0.2v) operating current: random read/write average power supply current i cc 3 205 195 185 ma 4, 40 (ras#, cas#, address cycling: t rc = t rc [min]) operating current: edo page mode average power supply current i cc 4 125 120 115 ma 4, 40 (ras# = v il , cas#, address cycling: t pc = t pc [min]; t cp, t asc = 10ns) refresh current: ras#-only average power supply current i cc 5 205 195 185 ma 4 (ras# cycling, cas#=v ih : t rc = t rc [min]) refresh current: cbr average power supply current i cc 6 180 170 160 ma 4, 5 (ras#, cas#, address cycling: t rc = t rc [min]) absolute maximum ratings* voltage on any pin relative to v ss ..................... -1v to +7v operating temperature, t a (ambient) .......... 0 c to +70 c storage temperature (plastic) .................... -55 c to +150 c power dissipation .......................................................... 1.2w short circuit output current ..................................... 50ma *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. electrical characteristics and recommended dc operating conditions (notes: 1, 6, 7) (v cc = +5v 10%)** parameter/condition symbol min max units notes supply voltage v cc ** 4.5 5.5 v input high (logic 1) voltage, all inputs v ih 2.4 v cc +1 v input low (logic 0) voltage, all inputs v il -1.0 0.8 v input leakage current any input 0v v in v cc +1.0v i i -2 2 m a3 (all other pins not under test = 0v) output leakage current (q is disabled; 0v v out v cc )i oz -10 10 m a output levels v oh 2.4 v output high voltage (i out = -2.5ma) output low voltage (i out = 2.1ma) v ol 0.4 v max **40 and 50ns specifications are limited to a v cc range of 5%.
8 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. electrical characteristics and recommended ac operating conditions (notes: 6, 7, 8, 9, 10, 11, 12, 13) (v cc = +5v 10%)* ac characteristics -4 -5 -6 parameter sym min max min max min max units notes access time from column-address t aa 20 25 30 ns column-address setup to cas# t ach 15 15 15 ns precharge during write column-address hold time (referenced to ras#) t ar 30 40 40 ns column-address setup time t asc 0 0 0 ns 29 row-address setup time t asr 0 0 0 ns column-address to we# delay time t awd 37 48 55 ns 21 access time from cas# t cac 12 15 15 ns 15, 31 column-address hold time t cah 7 8 10 ns 29 cas# pulse width t cas 6 10,000 8 10,000 10 10,000 ns 37 cas# hold time (cbr refresh) t chr 10 10 10 ns 5, 30 last cas# going low to first cas# t clch 10 10 10 ns 32 returning high cas# to output in low-z t clz 3 3 3 ns 31, 41 data output hold after cas# low t coh 3 3 3 ns cas# precharge time t cp 6 8 10 ns 16, 34 access time from cas# precharge t cpa 25 28 35 ns 31 cas# to ras# precharge time t crp 5 5 5 ns 30 cas# hold time t csh 37 40 45 ns 30 cas# setup time (cbr refresh) t csr 10 10 10 ns 5, 29 cas# to we# delay time t cwd 30 35 40 ns 21, 29 write command to cas# lead time t cwl 7 8 10 ns 26, 30 data-in hold time t dh 7 8 10 ns 22, 31 data-in setup time t ds 0 0 0 ns 22, 31 output disable time t od 3 15 3 15 3 15 ns 28, 39, 41 output enable time t oe 10 15 15 ns 23, 31 oe# hold time from we# during t oeh 6 10 15 ns 27 read-modify-write cycle oe# high hold time from cas# high t oehc 10 10 10 ns oe# high pulse width t oep 10 10 10 ns oe# low to cas# high setup time t oes 5 5 5 ns output buffer turn-off delay from t off 3 15 3 15 3 15 ns 20, 28, cas# or ras# 31, 41 capacitance parameter symbol max units notes input capacitance: a0-a8 c i 1 5pf2 input capacitance: ras#, casl#, cash#, we#, oe# c i 2 7pf2 input/output capacitance: dq c io 7pf2 *40ns and 50ns specifications are limited to a v cc range of 5%.
9 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. electrical characteristics and recommended ac operating conditions (notes: 6, 7, 8, 9, 10, 11, 12, 13) (vcc = +5v 10%)* ac characteristics -4 -5 -6 parameter sym min max min max min max units notes oe# setup prior to ras# during t ord 0 0 0 ns hidden refresh cycle edo-page-mode read or write cycle time t pc 15 20 25 ns 33 edo-page-mode read-write cycle time t prwc 60 65 72 ns 33 access time from ras# t rac 40 50 60 ns 14 ras# to column-address delay time t rad 7 13 15 ns 18 row-address hold time t rah 7 10 10 ns column-address to ras# lead time t ral 15 17 22 ns ras# pulse width t ras 40 10,000 50 10,000 60 10,000 ns ras# pulse width (edo page mode) t rasp 40 100,000 50 100,000 60 100,000 ns random read or write cycle time t rc 70 100 110 ns ras# to cas# delay time t rcd 17 18 20 ns 17, 29 read command hold time (referenced to cas#) t rch 0 0 0 ns 19, 26, 30 read command setup time t rcs 0 0 0 ns 26, 29 refresh period (512 cycles) t ref 8 8 8 ms ras# precharge time t rp 25 30 35 ns ras# to cas# precharge time t rpc 10 10 10 ns read command hold time (referenced to ras#) t rrh 0 0 0 ns 19 ras# hold time t rsh 7 8 10 ns 38 read write cycle time t rwc 105 126 140 ns ras# to we# delay time t rwd 60 69 85 ns 21 write command to ras# lead time t rwl 7 8 10 ns 26 transition time (rise or fall) t t 1 50 2 50 2 50 ns 9, 10 write command hold time t wch 7 8 10 ns 26, 38 write command hold time (referenced to ras#) t wcr 30 40 40 ns 26 write command setup time t wcs 0 0 0 ns 21, 26, 29 output disable delay from we# t whz 3 13 3 13 3 15 ns write command pulse width t wp 7 8 10 ns 26 we# pulse widths to disable outputs t wpz 10 10 10 ns we# hold time (cbr refresh) t wrh 10 10 10 ns we# setup time (cbr refresh) t wrp 10 10 10 ns *40ns and 50ns specifications are limited to a v cc range of 5%.
10 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v cc = 4.75v; f = 1 mhz. 3. nc pins are assumed to be left floating and are not tested for leakage. 4. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the output open. 5. enables on-chip refresh and address counters. 6. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 c t a 70 c) is assured. 7. an initial pause of 100 m s is required after power-up followed by eight ras# refresh cycles (ras#-only or cbr) before proper device operation is assured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 8. ac characteristics assume t t = 2ns. 9. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 10. in addition to meeting the transition rate specifica- tion, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 11. if cas# and ras# = v ih , data output is high-z. 12. if cas# = v il , data output may contain data from the last valid read cycle. 13. measured with a load equivalent to one ttl gate and 50pf, v ol = 0.8v and v oh = 2.0v. 14. assumes that t rcd < t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 15. assumes that t rcd 3 t rcd (max). 16. if cas# is low at the falling edge of ras#, q will be maintained from the previous cycle. to initiate a new cycle and clear the q buffer, cas# and ras# must be pulsed high for t cp. 17. the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac [ t rac (min) no longer applied]. with or without the t rcd (max) limit, t aa (min), t rac (min) and t cac (min) must always be met. 18. the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa [ t rac (min) and t cac (min) no longer applied]. with or without the t rad (max) limit, t aa (min), t rac (min) and t cac (min) must always be met. 19. either t rch or t rrh must be satisfied for a read cycle. 20. t off (max) defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . 21. t wcs, t rwd, t awd and t cwd are restrictive operating parameters in late write and read- modify-write cycles only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain an open circuit throughout the entire cycle. if t rwd 3 t rwd (min), t awd 3 t awd (min) and t cwd 3 t cwd (min), the cycle is a read-write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of q (at access time and until cas# and ras# or oe# go back to v ih ) is indeterminate. oe# held high and we# taken low after cas# goes low result in a late write (oe#- controlled) cycle. 22. these parameters are referenced to cas# leading edge in early write cycles and we# leading edge in late write or read-modify-write cycles. 23. during a read cycle, if oe# is low then taken high before cas# goes high, q goes open. if oe# is tied permanently low, a late write or read- modify-write operation is not possible. 24. a hidden refresh may also be performed after a write cycle. in this case, we# = low and oe# = high. 25. all other inputs at v cc -0.2v. 26. write command is defined as we# going low. 27. late write and read-modify-write cycles must have both t od and t oeh met (oe# high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the dqs will provide the previously written data if cas# remains low and oe# is taken back low after t oeh is met.
11 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. notes (continued) 28. the dqs open during read cycles once t od or t off occur. 29. the first cas#x edge to transition low. 30. the last cas#x edge to transition high. 31. output parameter (dqx) is referenced to correspond- ing cas# input, dq1-dq8 by casl# and dq9-dq16 by cash#. 32. last falling cas#x edge to first rising cas#x edge. 33. last rising cas#x edge to next cycles last rising cas#x edge. 34. last rising cas#x edge to first falling cas#x edge. 35. first dqs controlled by the first cas#x to go low. 36. last dqs controlled by the last cas#x to go high. 37. each cas#x must meet minimum pulse width. 38. last cas#x to go low. 39. all dqs controlled, regardless casl# and cash#. 40. column address changed once each cycle. 41. the 3ns minimum is a parameter guaranteed by design.
12 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. read cycle note: 1. t off is referenced from the rising edge of ras# or cas#, whichever occurs last. -4 -5 -6 sym min max min max min max units t off 315 315 315ns t rac 40 50 60 ns t rad 7 13 15 ns t rah 7 10 10 ns t ral 15 17 22 ns t ras 40 10,000 50 10,000 60 10,000 ns t rc 75 100 110 ns t rcd 17 18 20 ns t rch 0 0 0 ns t rcs 0 0 0 ns t rp 25 30 35 ns t rrh 0 0 0 ns t rsh 8 10 15 ns timing parameters -4 -5 -6 sym min max min max min max units t aa 20 25 30 ns t ar 30 40 40 ns t asc 0 0 0 ns t asr 0 0 0 ns t cac 12 15 15 ns t cah 7 8 10 ns t cas 6 10,000 8 10,000 10 10,000 ns t clch 10 10 10 ns t clz 3 3 3 ns t crp 5 5 5 ns t csh 37 40 40 ns t od 315 315 315ns t oe 10 15 15 ns t oes 5 5 5 ns t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t ral t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe t oes oe# v v ih il column t clch cash#/casl# we# note 1 don? care undefined
13 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. early write cycle don? care undefined v v ih il valid data row column row t ds t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ral t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t dh t clch we# casl#/cash# t ach timing parameters -4 -5 -6 sym min max min max min max units t ach 15 15 15 ns t ar 30 40 40 ns t asc 0 0 0 ns t asr 0 0 0 ns t cah 7 8 10 ns t cas 6 10,000 8 10,000 10 10,000 ns t clch 10 10 10 ns t crp 5 5 5 ns t csh 37 40 40 ns t cwl 7 8 10 ns t dh 7 8 10 ns t ds000ns t rad 7 13 15 ns t rah 7 10 10 ns t ral 15 17 22 ns t ras 40 10,000 50 10,000 60 10,000 ns t rc 75 100 110 ns t rcd 17 18 20 ns t rp 25 30 35 ns t rsh 7 8 10 ns t rwl 7 8 10 ns t wch 7 8 10 ns t wcr 30 40 40 ns t wcs 0 0 0 ns t wp 7 8 10 ns -4 -5 -6 sym min max min max min max units
14 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. read write cycle (late write and read-modify-write cycles) valid d out valid d in row column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t ral t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe# t oeh t clch we# casl#/cash# t ach don? care undefined t od 315 315 315ns t oe 10 15 15 ns t oeh 6 10 15 ns t rac 40 50 60 ns t rad 7 13 15 ns t rah 7 10 10 ns t ral 15 17 22 ns t ras 40 10,000 50 10,000 60 10,000 ns t rcd 17 18 20 ns t rcs 0 0 0 ns t rp 25 30 35 ns t rsh 7 8 10 ns t rwc 105 126 140 ns t rwd 60 69 85 ns t rwl 7 8 10 ns t wp 7 8 10 ns timing parameters -4 -5 -6 sym min max min max min max units t aa 30 25 30 ns t ach 15 15 15 ns t ar 30 40 40 ns t asc 0 0 0 ns t asr 0 0 0 ns t awd 37 48 55 ns t cac 12 15 15 ns t cah 7 8 10 ns t cas 6 10,000 8 10,000 10 10,000 ns t clch 10 10 10 ns t clz 3 3 3 ns t crp 5 5 5 ns t csh 37 40 40 ns t cwd 30 35 40 ns t cwl 7 8 10 ns t dh 7 8 10 ns t ds000ns -4 -5 -6 sym min max min max min max units
15 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. edo-page-mode read cycle valid data valid data valid data column column column row row don? care undefined t od t cah t asc t ral t cp t rsh t cp t cp t cas, t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rrh t rch t off t cac t cpa t aa t clz t cac t cpa t aa t cac t rac t aa t clz t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v oh ol v v ih il ras# oe# t clch t cas, t clch t cas, t clch cash#/casl# we# t coh t oep t oehc t oes t oes (note 1) note: 1. t pc can be measured from falling edge of cas# to falling edge of cas#, or from rising edge of cas# to rising edge of cas#. both measurements must meet the t pc specification. -4 -5 -6 sym min max min max min max units t oehc 10 10 10 ns t oep 10 10 10 ns t oes 5 5 5 ns t off 315 315 315 ns t pc 15 20 25 ns t rac 40 50 60 ns t rad 7 13 15 ns t rah 7 10 10 ns t ral 15 17 22 ns t rasp 40 100,000 50 100,000 60 100,000 ns t rcd 17 18 20 ns t rch 0 0 0 ns t rcs 0 0 0 ns t rp 25 30 35 ns t rrh 0 0 0 ns t rsh 7 8 10 ns timing parameters -4 -5 -6 sym min max min max min max units t aa 20 25 30 ns t ar 30 40 40 ns t asc 0 0 0 ns t asr 0 0 0 ns t cac 12 15 15 ns t cah 7 8 10 ns t cas 6 10,000 8 10,000 10 10,000 ns t clch 10 10 10 ns t clz 3 3 3 ns t coh 3 3 3 ns t cp 6 8 10 ns t cpa 25 28 35 ns t crp 5 5 5 ns t csh 37 40 40 ns t od 315 315 315ns t oe 10 15 15 ns
16 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. edo-page-mode early-write cycle t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t ral t cah t asc t cah t asc t rah t asr t rad t ar column column column row row t cp t rsh t cp t cp t rcd t crp t pc t csh t rasp t rp v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t cas, t clch t cas, t clch t cas, t clch we# casl#/cash# t ach t ach t ach don? care undefined -4 -5 -6 sym min max min max min max units timing parameters -4 -5 -6 sym min max min max min max units t ach 15 15 15 ns t ar 30 40 40 ns t asc 0 0 0 ns t asr 0 0 0 ns t cah 7 8 10 ns t cas 6 10,000 8 10,000 10 10,000 ns t clch 10 10 10 ns t cp 6 8 10 ns t crp 5 5 5 ns t csh 37 40 40 ns t cwl 7 8 10 ns t dh 7 8 10 ns t ds000ns t pc 15 20 25 ns t rad 7 13 15 ns t rah 7 10 10 ns t ral 15 17 22 ns t rasp 40 100,000 50 100,000 60 100,000 ns t rcd 17 18 20 ns t rp 25 30 35 ns t rsh 7 8 10 ns t rwl 7 8 10 ns t wch 7 8 10 ns t wcr 30 40 40 ns t wcs 0 0 0 ns t wp 7 8 10 ns
17 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. edo-page-mode read-write cycle (late write and read-modify-write cycles) don? care undefined t t od t oe t od t oe t od t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t ral t cp t rsh t cp t rp t rasp t cp t rcd t csh t pc t crp row column column column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t prwc oeh t cas, t clch t cas, t clch t cas, t clch we# cas#l/cash# note 1 note: 1. t pc can be measured from falling edge to falling edge of cas#, or from rising edge to rising edge of cas#. both measurements must meet the t pc specification. timing parameters -4 -5 -6 sym min max min max min max units t aa 20 25 30 ns t ar 30 40 40 ns t asc 0 0 0 ns t asr 0 0 0 ns t awd 37 48 55 ns t cac 12 15 15 ns t cah 7 8 10 ns t cas 6 10,000 8 10,000 10 10,000 ns t clch 10 10 10 ns t clz 3 3 3 ns t cp 6 8 10 ns t cpa 25 28 35 ns t crp 5 5 5 ns t csh 37 40 40 ns t cwd 30 35 40 ns t cwl 7 8 10 ns t dh 7 8 10 ns t ds000ns -4 -5 -6 sym min max min max min max units t od 315 315 315ns t oe 10 15 15 ns t oeh 6 10 15 ns t pc 15 20 25 ns t prwc 60 65 72 ns t rac 40 50 60 ns t rad 7 13 15 ns t rah 7 10 10 ns t ral 15 17 22 ns t rasp 40 100,000 50 100,000 60 100,000 ns t rcd 17 18 20 ns t rcs 0 0 0 ns t rp 25 30 35 ns t rsh 7 8 10 ns t rwd 60 69 85 ns t rwl 7 8 10 ns t wp 7 8 10 ns
18 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. edo-page-mode read-early-write cycle (psuedo read-modify-write) v v ih il v v ih il ras# v v ih il addr v v ih il we# t rasp t rp row column (a) column (n) row v v ih il oe# v v ioh iol t crp t csh t cas t rcd t asr t rah t rad t asc t ar t cah t asc t cah t asc t cah t ral t cp t cas t cp t rsh t cas t cp valid data in t rcs t rch t wcs t oe valid data (b) valid data (a) t whz t cac t cpa t aa t cac t aa open dq t pc rac t t coh t wch t ds t dh t pc column (b) t ach don? care undefined casl#/cash# -4 -5 -6 sym min max min max min max units t oe 10 15 15 ns t pc 15 20 25 ns t rac 40 50 60 ns t rad 7 13 15 ns t rah 7 10 10 ns t ral 15 17 22 ns t rasp 40 100,000 50 100,000 60 100,000 ns t rcd 17 18 20 ns t rch 0 0 0 ns t rcs 0 0 0 ns t rp 25 30 35 ns t rsh 7 8 10 ns t wch 7 8 10 ns t wcs 0 0 0 ns t whz313 313 315ns timing parameters -4 -5 -6 sym min max min max min max units t aa 20 25 30 ns t ach 15 15 15 ns t ar 37 40 40 ns t asc 0 0 0 ns t asr 0 0 0 ns t cac 12 15 15 ns t cah 7 8 10 ns t cas 6 10,000 8 10,000 10 10,000 ns t coh 3 3 3 ns t cp 6 8 10 ns t cpa 25 28 35 ns t crp 5 5 5 ns t csh 37 40 40 ns t dh 7 8 10 ns t ds000ns
19 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. read cycle (with we#-controlled disable) t clz t cac t rac t aa valid data open t rch t rcs t asc t rah t rad t ar t cah t rcd t cas t csh t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column we# t whz t wpz t cp t asc t rcs column t clz don? care undefined note 1 t wrp t wrh casl#/cash# note: 1. although we# is a dont care at ras# time during an access cycle (read or write), the system designer should implement we# high for t wrp and t wrh. this design implementation will facilitate compatibility with future edo drams. -4 -5 -6 sym min max min max min max units t oe 10 15 15 ns t rac 40 50 60 ns t rad 7 13 15 ns t rah 7 10 10 ns t rch 0 0 0 ns t rcd 17 18 20 ns t rcs 0 0 0 ns t whz313 313 315ns t wpz 10 10 10 ns t wrh 10 10 10 ns t wrp 10 10 10 ns timing parameters -4 -5 -6 sym min max min max min max units t aa 20 25 30 ns t ar 30 40 40 ns t asc 0 0 0 ns t asr 0 0 0 ns t cac 12 15 15 ns t cah 7 8 10 ns t cas 6 10,000 8 10,000 10 10,000 ns t clz 3 3 3 ns t cp 6 8 10 ns t crp 5 5 5 ns t csh 37 40 40 ns t od 315 315 315ns
20 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. ras#-only refresh cycle (oe#, we# = dont care) row v v ih il v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open q v v oh ol t rpc casl#/cash# we# v v ih il t wrh t wrp t wrh t wrp note 1 t rp v v ih il v v ih il ras# t ras open t chr t csr v v ih il v v oh ol dq t rp t ras t rpc t csr t rpc t chr t cp cash#, casl# we# don? care undefined cbr refresh cycle (addresses; oe# = dont care) -4 -5 -6 sym min max min max min max units t ras 40 10,000 50 10,000 60 10,000 ns t rc 75 100 110 ns t rp 25 30 35 ns t rpc 10 10 10 ns t wrh 10 10 10 ns t wrp 10 10 10 ns timing parameters -4 -5 -6 sym min max min max min max units t asr 0 0 0 ns t chr 10 10 10 ns t cp 6 8 10 ns t crp 5 5 5 ns t csr 10 10 10 ns t rah 7 10 10 ns note: 1. although we# is a dont care at ras# time during an access cycle (read or write), the system designer should implement we# high for t wrp and t wrh. this design implementation will facilitate compatibility with future edo drams.
21 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. hidden refresh cycle 24 (we# = high; oe# = low) don? care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t ral t crp t rcd t rsh t ras t rp t chr t ras dqx v v oh ol v v ih il addr v v ih il v v ih il ras# v v ih il t oe t od oe# t ord note 1 casl#/cash# timing parameters -4 -5 -6 sym min max min max min max units t aa 20 25 30 ns t ar 30 40 40 ns t asc 0 0 0 ns t asr 0 0 0 ns t cac 12 15 15 ns t cah 7 8 10 ns t chr 10 10 10 ns t clz 3 3 3 ns t crp 5 5 5 ns t od 315 315 315ns t oe 10 15 15 ns -4 -5 -6 sym min max min max min max units t off 315 315 315 ns t ord 0 0 0 ns t rac 40 50 60 ns t rad 7 13 15 ns t rah 7 10 10 ns t ral 15 17 22 ns t ras 40 10,000 50 10,000 60 10,000 ns t rcd 17 18 20 ns t rp 25 30 35 ns t rsh 7 8 10 ns note: 1. t off is referenced from the rising edge of ras# or cas#, whichever occurs last.
22 MT4C16270 micron technology, inc., reserves the right to change products or specifications without notice. w06.pm5 C rev. 10/96 ? 1996, micron technology, inc. MT4C16270 256k x 16 dram technology, inc. 40-pin plastic soj (400 mil) da-6 .399 (10.13) .405 (10.29) 1.023 (25.98) .445 (11.30) .050 (1.27) typ pin #1 index .020 (0.51) .015 (0.38) .025 (0.64) min .380 (9.65) seating plane 1.029 (26.14) .950 (24.13) .360 (9.14) .435 (11.05) .090 (2.29) .105 (2.67) .150 (3.81) .138 (3.51) .037 (0.94) max dambar protrusion .026 (0.66) .032 (0.81) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900, micron datafax: 208-368-5800 e-mail: prodmktg@micron.com , internet: http://www.micron.com , customer comment line: 800-932-4992

▲Up To Search▲

Price & Availability of MT4C16270

	To Download MT4C16270 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .